analogdevicesinc / hdl
HDL libraries and projects
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HDL libraries and projects
Verilog Configurable Cache
PicoRV32 - A Size-Optimized RISC-V CPU
The USRP™ Hardware Driver Repository
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Open source FPGA-based NIC and platform for in-network compute
An Open-source FPGA IP Generator