lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Common SystemVerilog components
RISC-V Debug Support for our PULP RISC-V Cores
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A Linux-capable RISC-V multicore for and by the world
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
BaseJump STL: A Standard Template Library for SystemVerilog